The PCI Express™ interface protocol, as defined by the PCI Express Base Specification, Revision 1.0a (Apr. 15, 2003), is fast becoming a widely used standard across the computer industry for a high-speed data communication link. A PCI-Express™ link is made of one or more lanes. A single lane is a full-duplex (i.e. 2-way) differential serial interconnection between two devices. Each device that is coupled to the link has a transmitter and a receiver in each lane of the link. A multi-lane PCI-Express™ link is very modifiable because each lane can actually become a complete link to transfer information. For example, on a x16 link has 16 independent full-duplex serial lanes. It is possible to shut down 15 lanes and keep a fully operational two-way interconnect running between two devices with the remaining single operational lane. Devices in modern computers have become quite computationally powerful. This has increased performance, but it also tends to increase power consumption. Power savings per device is important in almost any computer system produced today. It is beneficial in a modern computer system to save as much power as possible. These savings can come from the processor, the motherboard, as well as any peripheral devices that are plugged into one or more links present in the computer system. Power savings on the PCI-Express™ link could provide significant system power savings. Additionally, though PCI-Express™ is one of the most common multi-lane serial links in the industry today, future multi-lane serial links as well as the peripheral devices they connect, would also benefit from power savings.